This invention pertains to three dimensional integrated circuits, apparatuses, and methods for fabricating three-dimensional integrated circuits; more specifically this invention relates to three-dimensional integrated circuits and methods of interconnect metallization for three-dimensional integrated circuits.
A three-dimensional integrated circuit includes two or more semiconductor chips with integrated circuits or includes two or more semiconductor wafers with integrated circuits. The semiconductor chips or semiconductor wafers are stacked together, bonded, and electrically interconnected in three dimensions, i.e., integrated within the semiconductor chips or semiconductor wafers and integrated between the semiconductor chips or semiconductor wafers. The interconnections between the chips or between the wafers are accomplished by way of through holes from the back side to the front side of one or more of the chips or one or more of the semiconductor wafers. In other words, the electrical connections between the stack of chips or stack of wafers are made by way of the through holes. Three-dimensional integrated circuits have at least one and may have a large number of through holes for interconnect metallization between the semiconductor chips or between the semiconductor wafers.
Three-dimensional integrated circuits, according to some designs, will use through-hole vias that are large, high aspect ratio features with dimensions an order of magnitude or more larger than the minimum geometry features for standard technology dual damascene metallization interconnects. Standard technology electroplating chemistry for metallization of semiconductor devices is designed for bottom-up void free fill. The standard technology electrochemical bottom-up void free fill may not be suitable for bottom-up filling of large, high aspect ratio features required for some through-hole vias.
An alternative to the electrochemical bottom-up void free fill is to use a conformal electrochemical deposition process to fill the through hole vias. Standard technology processes for conformal electrochemical deposition often result in a seam or a closed void which can trap the electrochemical process liquids. Trapped electrochemical process liquids can cause problems such as corrosion of the integrated circuit. Another possible problem of having the process liquids trapped in the integrated circuit is that the liquids may be vaporized during subsequent process steps, especially those at high temperature or low pressure, and result in physical damage to the integrated circuit.
Clearly, all of the requirements for fabricating three-dimensional integrated circuits cannot be met using standard two-dimensional integrated circuit fabrication technology. The practical fabrication of high reliability three-dimensional integrated circuits will require new processes capable of meeting the requirements for metallization of three-dimensional integrated circuits. More specifically, there is a need for new processes capable of meeting the unusual aspect ratio requirements for three-dimensional integrated circuits while allowing deposition of metal layers for high reliability and high-performance devices.